\subsubsection{Architecture Design}
Proposals such as Razor~\cite{Razor} and ReCycle~\cite{ReCycle_ISCA07}
aimed to address the effects of process variability at the
architecturally visible level. Designing for worst-case scenarios in
variability results in highly over-engineered guardbands, either in
timing or supply voltage. The worst-case paths through circuits are
often not exercised by common case code execution, so a design
augmented with error-detection logic(e.g. Razor latches) for timing
violations can relax guardbands. Similarly, the variation effects in
any particular portion of the design may be greater or lesser than
expected. Approaches such as ReCycle aim to dynamically re-tune a
particular chip's pipeline by stealing time from less affected
pipeline stages to give to more variation-degraded stages in order to
allow the chip to operate closer to a frequency representative of the
average impact of variation, rather than the worst-case impact.

However, both of the above approaches require re-evaluation when
embodied in TFET processors. The Razor mechanism for error detection
relies on high confidence concerning the delay differential between
the early and late portions of the latch. However, as mentioned in
Section~\ref{sec:circuit_design}, traditional state-elements are among
those that must be redesigned for the CMOS to TFET
transition. Additionally, as variability increases at lower voltages,
the guardbanding required to maintain confidence regarding the
separation in time between the early and late portions of the latch
will increase, providing back-pressure as to how much variability the
entire dual-timed latch design can tolerate.

Similarly, techniques such as ReCycle that aim to tune particular
chips to their exhibited variability rely on the capability to
accurately characterize the effects of variability within a chip. This
not only requires an ability to accurately estimate many paths via a
small number of proxy circuits, but also assumes that the measurements
of these paths are history-independent. As recent research has hinted at
history-dependent performance effects in TFET devices (e.g. the
switching activity of a circuit is dependent on the both the ratio and
temporal nature of logic ones and zeros passed into it), we will have
to devise TFET-specific variants of these proxy-techniques for
pipeline level tuning.